1. Field of the Invention
The present invention relates to an interface apparatus and, more specifically, to a data transmitting apparatus which can increase an amount of data transmission per unit time.
2. Description of the Background Art
Information processed or to be processed by information processing apparatuses such as computers and facsimiles are transmitted to and from such information processing apparatuses which are remote from each other by utilizing a data transmission system, including a transmission path provided between the information processing apparatuses and a transmitter which is called a data circuit terminating equipment (DCE).
The data circuit terminating equipment is provided between the transmission path and a computer, an input/output device or the like (hereinafter referred to as a data terminal equipment) constituting the information processing apparatus to be connected by the data transmission system, and carries out mutual conversion of signal conditions between the data terminal equipment and the transmission path.
The method of data transmission by the data transmission system includes a serial transmission method in which plural bits of data are transmitted bit by bit in time sequence through one transmission path, and a parallel transmission method in which the plural bits of data are transmitted over the transmission path at one time.
The serial transmission method does not require a plurality of signal lines as the transmission path, while the parallel transmission method requires, as the transmission path, signal lines the number of which is the same as the number of bits of data to be transmitted at one time.
In the data transmission system, the transmission path and the data circuit terminating equipment constitute an interface apparatus for connection between information processing apparatuses.
Generally, data is divided into groups each having a predetermined bit length, which are called packets, and transmitted/received packet by packet.
In the data transmission system, transmission is controlled in accordance with a so called handshaking system, a synchronous system or the like. In the handshaking system, at the time of transmission of each packet, a control signal indicative of the start of transmission is sent from the transmitter on the transmitting side to the transmitter of the receiving side. When the packet is received by the transmitter on the receiving side, a control signal indicative of the reception of this packet is sent from the transmitter on the receiving side to the transmitter on the transmitting side, and thus data transmission/reception between data terminal equipments is acknowledged. In the synchronous system, a clock signal having a predetermined frequency which corresponds to the length of time period allotted to each bit of the data to be transmitted is used between the transmitters of the receiving side and the transmitting side, so that the timing of transmission and reception of data is synchronized.
FIG. 53 is a schematic block diagram showing a structure of a conventional interface apparatus in which transmission is controlled in accordance with the handshaking system. Referring to FIG. 53, the interface apparatus is provided between two data terminal equipments each having a CPU (Central Processing Unit) as an apparatus for effecting data processing, and transmits data of n bits in parallel between the data terminal equipments.
FIG. 54 is a timing chart showing data transmission timing of the interface apparatus shown in FIG. 54.
The structure and operation of the conventional interface apparatus will be described with reference to FIGS. 53 and 54.
Referring to FIG. 53, the interface apparatus 900 includes a transmitting side data transmitter 920 connected to a transmitting side data terminal equipment 902, a receiving side data transmitter 922 connected to a receiving side data terminal equipment 904, and n data signal lines DL1 to DLn and control signal lines CL1 and CL2 connected between the transmitting side data transmitter 920 and the receiving side data transmitter 922. These data signal lines DL1 to DLn and control signal lines CL1 and CL2 constitute a transmission path 300.
The transmitting side data transmitter 920 includes a data holding mechanism 930 for temporarily storing n bits of data applied at one time from transmitting side data terminal equipment 902 and for supplying the data to data signal lines DL1 to DLn, and a transfer control mechanism 932 responsive to a control signal supplied through control signal line CL2 and a control signal supplied from the transmitting side data terminal equipment 902 for controlling data holding mechanism 930.
The receiving side data transmitter 922 includes a data holding mechanism 950 for temporarily storing n bits of data supplied at one time through data signal lines DL1 to DLn and for supplying the data to the receiving side data terminal equipment 904, and a transfer control mechanism 952 responsive to a control signal supplied through control signal line CL1 and a control signal supplied from the receiving side data terminal equipment 904 for controlling data holding mechanism 950.
It is assumed that the CPU 906 in the transmitting side data terminal equipment 902 and CPU 908 in the receiving side data terminal equipment are capable of processing n bits of data at one time.
When data which is to be transmitted to data terminal equipment 904 is generated in data terminal equipment 902, the data is applied to the transmitting side data transmitter 920 on the basis of n bits by n bits under the control of CPU 906.
In the following description, the data group including n bits is called a word.
When data transmitter 920 is capable of taking one word of data transmitted from data terminal equipment 902, that is, when a control signal SRO to the transmitting side data terminal equipment 902 indicates a transmission permitting state, CPU 906 of transmitting side data terminal equipment 902 generates a transmission request so that one word is supplied to data transmitter 920 and at the same time, a control signal SSO is input from data terminal equipment 902 to transfer control mechanism 932 of data transmitter 920.
Transfer control mechanism 932 sets the control signal SRO at a receiving state so as to indicate reception of data to data terminal equipment 902 in response to control signal SSO. This change of the control signal SRO is referred to as ACKNOWLEDGE signal (hereinafter simply referred to as "ACK" signal).
The control signal SRO indicates, at the receiving state, that it is now receiving the data transmitted from the data terminal equipment 902, and signals the data terminal equipment 902 that transmission of the next data is inhibited as it is receiving data. More specifically, control signal SRO assumes a transmission permitting state which shows the transmitter side circuit that the receiving side circuit is permitted to take data in, and a receiving state (which is also referred to as transmission inhibited state) which shows the transmitting side circuit that the receiving side circuit is now receiving data and the transmission of the next data is inhibited.
Similarly, a control signal /RI applied from the receiving side data transmitter 922 through control signal line CL2 to data transmitter 920 assumes a transmission permitting state indicating that the data transmitter 922 is capable of taking data from data transmitter 922, and a receiving state indicating that the data transmitter 922 is receiving data and transmission of the next data from data transmitter 920 is inhibited.
In the specification, "/" added to a reference character indicative of a signal means that the signal is low active. This corresponds to the reference character with an over bar in the drawings.
Transfer control mechanism 932 controls data holding mechanism 930 such that data transmission from data transmitter 920 to data transmitter 922 starts in response to the control signal /R1 from data transmitter 922 which has changed to the transmission permitting state.
In this manner, transfer control mechanism 932 instructs data holding mechanism 930 to take and store n bits of data, when control signal /RI from data transmitter 922 is at the transmission permitting state, in response to control signal SSO, outputs a control signal /CO indicative of the start of data transmission to data transmitter 922, and changes control signal SRO from the receiving state to transmission permitting state so that the data transmitter 920 is set to a standby state in which data from data equipment 902 can be received. Thus, data holding mechanism 930 outputs one word from data terminal equipment 902 to an output buffer 934, n bits of data constituting one word are transmitted to n data signal lines DL1 to DLn at one time through output buffer 934, and a transmission signal is transmitted through output buffer 936 to control signal line CL1. In the following, control signals SSO, SSI, /CI and /CO are also referred to as transmission signals.
In this example, the transmission signal is a low active signal, and indicates, when it attains the low level, that the data is transmitted from transmitting side equipment to the receiving side equipment.
The n bits of data DO transmitted over data signal lines Dl1 to DLn are input to data holding mechanism 950 through an input buffer 954 at the receiving side transmitter 922. Meanwhile, the transmission signal /CO transmitted over control signal line CL1 is input to transfer control mechanism 952 through input buffer 956 at the receiving side data transmitter 922.
Transfer control mechanism 952 sets the control signal /RO (/RI) to transmitting side data transmitter 920 at a receiving state, in response to the transmission signal /CI from input buffer 956 (that is, an output signal /CO of output buffer 936 of the transmitting side data transmitter 920).
Therefore, when n bits of data from data transmitter 920 are received by data transmitter 922, the control signal /RI is switched to the transmission inhibiting state in the transmitting side data transmitter 920. The transmitting side transfer control mechanism 932 detects, upon switching of control signal /RI to the transmission inhibited state, the fact that the data transmitter 922 has received the data from the data transmitter 920, and terminates the transmission signal.
When control signal SRI from data terminal equipment 904 is at the transmission permitting state, the receiving side transfer control mechanism 952 outputs to data terminal equipment 904, in response to transmission signal CI, control signal SSI indicative of the start of data transmission from data transmitter 920 to data terminal equipment 904. Transfer control mechanism 952 switches control signal /RO to data transmitter 920 from transmission inhibiting state to transmission permitting state, so that the data transmitter 922 is set to a standby state allowing reception of the next data from data transmitter 20. Approximately at the same time, transfer control mechanism 952 instructs data holding mechanism 950 to take and store n bits of data from input buffer 954.
CPU 908 in data terminal equipment 904 recognizes, in response to control signal SSI, that data transmitter 920 has received one word of data from data transmitter 920, and operates such that while data from data transmitter 922 is being received, the control signal SRI at the receiving state is input to receiving side transfer control mechanism 952. In this manner, control signal SRI assumes a transmission permitting state indicating that the data terminal equipment 904 is capable of receiving data from data transmitter 922, and a receiving state which indicates that the data terminal equipment 904 is now receiving data and transmission of the next data from data transmitter 922 is inhibited. In the following, control signals SRI, SRO, /RI and /RO are also referred to as reception signals.
When the reception signal SRI changes to the receiving state, the receiving side transfer control mechanism 952 recognizes that one word of data transmitted from data transmitter 920 are input through data signal lines DL1 to DLn to data transmitter 922 and to data terminal equipment 904 through data holding mechanism 950, and terminates data output from data holding mechanism 950 to data terminal equipment 904.
Data terminal equipment 904 switches reception signal SRI to data transmitter 922 from transmission inhibiting state to transmission permitting state in response to termination of reception and taking of data from data transmitter 922 so as to permit transmission of the next data from data transmitter 922, and enters the standby state, allowing reception of the next data.
In this example, the reception signal is also a low active signal. The reception signal attaining the low level shows the circuit receiving this reception signal that the data output from this circuit has been received by the circuit of the next stage, and that transmission of next data from this circuit should be inhibited. When the data is received by the circuit of the next stage and the circuit of the next stage becomes ready for the next data transmission, the reception signal attains to the high level. Therefore, the circuit on the transmitting side recognizes that the transmission of the next data is permitted as the reception signal is at the high level. Consequently, when there is a transmission request of new data from the circuit of the preceding stage, it can transmit the new data in response
In this manner, data transmission/reception is carried out in response to the control signals SSO and SRO between the transmitting side data terminal equipment 902 and the transmitting side data transmitter 920. Data transmission/reception is carried out in response to transmission signal /CO (/CI) and reception signal /RI RO between the transmitting side data transmitter 920 and the reception side data transmitter 922, and data transmission/reception is carried out in response to control signals SSI and SRI between the receiving side data transmitter 922 and the receiving side data terminal equipment 904.
More specifically, since data transmission/reception is carried out independently between the components on the transmitting side, between the transmitting side data transmitter and the receiving side data transmitter and between the receiving side components, data generated on the data terminal equipment 902 can be taken and processed word by word successively in the receiving side data terminal equipment 904.
After the lapse of a time period necessary for one word of data to be received and taken by data terminal equipment 904 from data terminal equipment 902 through data transmitters 920 and 922, and in a period (called one cycle time) until the start of transmission of the next one word of data from data terminal equipment 902, transmission signal /CO (/CI) attains at first to the low level at the start of data transmission from data transmitter 920 as shown in FIG. 54(a). During the time period .tau.1, the transmission signal /CO (/CI) is maintained at the low level until it returns to the high level in response to the reception signal /RI (/RO) attaining the low level, indicating that the data has been received and taken in data transmitter 922.
Reception signal /RI (/RO) attains to the low level by the operation of data transmitter 922 and data terminal equipment 904 in response to the low level transmission signal /CO (/CI), and maintained at the low level during the period .tau.3, until the data transmitter 922 starts transmission of data received from data transmitter 920 to the data terminal equipment 904 of the next stage, as shown in FIG. 54(b).
Transmission signal /CO (/CI) attains to the high level in response to a low level reception signal /RI (/RO) indicating that the data output from data transmitter 920 has been received by data transmitter 922. Thereafter, transmission signal /CO (/CI) is maintained at the high level during the period in which reception signal RI (/RO) returns to the high level allowing transmission of the next data from data transmitter 920 as the data transmitter 922 starts transmission of data to data terminal equipment 904. Transmission signal /CI (/CO) is at the high level during the period .tau.2 until the generation of the next data transmission request at the data terminal equipment 902 when the data transmitter 922 is at the standby state and ready for the reception of the next data from data transmitter 920.
More specifically, transmission signal /CO is kept at the low level during the period .tau.1 in which data transmitter 920 starts data transmission and a low level reception signal /RI (/RO) is returned from data transmitter 922, every time n bits of data, that is, one word is supplied from data terminal equipment 902 to data transmitter 920, or every time the control signal SSO is applied to transfer control mechanism 932. When it is recognized that data is transmitted from data transmitter 920 and the data is surely received by data transmitter 922, the transmission signal /CO is returned to the high level to be ready for the transmission of the next word from data transmitter 920 to data transmitter 922. Since reception signal /RO to data transmitter 920 is also returned to the high level simultaneously with the start of data transmission from data transmitter 922 to the data terminal equipment 904 of the next stage, data transmitter 920 starts transmission of the next data in response to any data transmission request from data terminal equipment 902 thereafter.
Transmission of data signals from data transmitter 920 to data signal lines DL1 to DLn is carried out in response to the fall of transmission signal /CO. Therefore, when a plurality of words to be transmitted to data terminal equipment 904 are continuously generated in data terminal equipment 902, data DO (DI) on data signal lines DL1 to DLn are switched to n bits of data constituting the next word in response to the fall of the transmission signal /CO, as shown in FIG. 54(c).
More specifically, at every one cycle time of transmission signal /CO, the first, the second . . . , kth, k+1th word, . . . appear on data signal lines DL1 to DLn.
Meanwhile, reception signal /RI attains to the low level in response to the application of the low level transmission signal /CO to transfer control mechanism 952 on the receiving side data transmitter 922, indicating that the data transmitter 922 has received one word of data from data transmitter 920. Therefore, as shown in FIG. 54(b), the reception signal /RI attains to and kept at the low level for a time period .tau.3, delayed from the fall of transmission signal /CO by the time period determined by the signal time on the control signal line CL1 and the time for signal processing in the data transmitter 922.
In the transmitting side data transmitter 920, transfer control mechanism 932 sets the control signal /CO back to the high level in response to the reception signal RI from input buffer 938 attaining the low level. Consequently, the transmitting side data transmitter 920 is ready for the transmission of the next word.
In the foregoing description, the interface apparatus 900 is provided between two data terminal equipments 902 and 904 which are distant from each other. Therefore, data transmitters 920 and 922 constituting the interface apparatus 900 are provided independent from the corresponding data terminal equipments 902 and 904 and the transmission path 300 is constituted by a cable 924 including at least (n+2) signal lines. The interface apparatus having such structure is used for data transmission between any circuits and apparatuses having data processing function, and the manner of provision of the data transmitters and the transmission path between these circuits or apparatuses is determined corresponding to the specific application.
As an example, assume that interface apparatus 900 of FIG. 53 is provided for data transmission between 1 chip semiconductor integrated circuit devices having data processing function. Namely, referring to FIG. 53, each of the data terminal equipments 902 and 904 is consisting formed on one semiconductor substrate. Data transmitter 920 is formed on the same semiconductor substrate as the circuitry constituting the data terminal equipment 902. Similarly, data transmitter 920 is formed on the same semiconductor substrate as the circuitry constituting the data terminal equipment 904. Namely, the transmitting side data terminal equipment 902 and the transmitting side data transmitter 920 are formed by one chip IC and the receiving side data terminal equipment 904 and the receiving side data transmitter 922 are formed by another one chip IC. Consequently, the transmission path 300 is formed by output pins of these ICs. Each of the data signal lines DL1 to DLn and each of the control signal lines CL1 and CL2 correspond to one output pin of the IC.
As described above, in the conventional interface apparatus, data transmission between two apparatuses (or circuits) having data processing function in accordance with the parallel transmission system is carried out on the basis of data unit each having a predetermined bit length over a plurality of data signal liens, the number of which is the same as the number of bits of data constituting one unit. In addition, transmission of data of each of the bits constituting one unit is carried out in a predetermined constant time period.
For this reason, if the amount of data transmitted in a unit time between apparatuses (or circuits having data processing function) is to be increased, the number of data signal lines between the data transmitters constituting the interface apparatus must be increased, or the speed of signal processing by the data transmitter itself must be improved.
Referring to FIG. 53, as methods for increasing the amount of data transmission per unit time between data terminal equipments 902 and 904, a method in which the number of bits which can be transmitted at one time from data transmitter 920 to data transmitter 922 is increased, and a method in which the time required for each bit of data to reach the data transmitter 922 through corresponding signal liens DL1 to DLn is reduced, have been proposed.
In order to increase the amount of data transmission per a unit time period by the former method, what is necessary is to increase the number n of data signal lines DL1 to DLn and to increase the number n of the input signal lines and the output signal lines of each of the data holding mechanism 930 and 950 for transmitting one word of data from data transmitter 920 to data transmitter 922 at one time.
If the number of such signal lines is increased to m times that of the prior art (m&gt;1), it becomes possible to transmit, in one cycle time of the transmission signal CO, (m.times.n) bits of data, that is, m words of data (assuming that the bit length of one word is n bits) at one time from data transmitter 920 to data transmitter 922. Therefore, the amount of data transmission per a unit time can be increased to m times that of the prior art.
In order to increase the amount of data transmission in unit time by the latter method, what is necessary is to reduce the time period (.tau.1+.tau.2) in which n bits of data constituting one word are on the data signal lines DL1 to DLn, by reducing one cycle time of the transmission signal /CO, as shown in FIG. 40.
For example, when the length of one cycle time of transmission signal /CO is reduced to 1/m (m&gt;1) that of the prior art, 1 word of data constituted by n bits can be transmitted from data transmitter 920 to data transmitter 922 for (m.times.k) times in the period (k.times.(.tau.1+.tau.2)) required in the prior art for transmitting one word of data constituted by n bits for k times from data transmitter 920 to data transmitter 922. Therefore, the amount of data transmission in a unit time can be increased to m times that of the prior art.
However, the speed of data transmission from data transmitter 920 to data transmitter 922 is determined by the characteristics of data signal lines DL1 to DLn, speed of data output and speed of signal processing in the transmitting side data transmitter 920, speed of processing the input data in the receiving side data transmitter 922 and so on, there is a limit in increasing the speed of data transmission.
More specifically, if one cycle time of transmission signal CO is reduced to be shorter than the time required for the 1 bit of data output from data holding mechanism 930 to be taken in the data holding mechanism 950 through output buffer 934, corresponding data signal lines DL1 to DLn and through the input buffer 954, then each bit of data transmitted from data transmitter 920 to data signal lines DL1 to DLn in response to the fall of transmission signal /CO cannot be completely taken in the receiving side data transmitter 922 by the next fall of the transmission signal /CO. Therefore, the length of 1 cycle time of transmission signal /CO must be the same or longer than this time period.
As described above, two approaches, that is, increase of the number of bits of data which can be transmitted at one time and reduction of time necessary for one data transmission between data transmitters have been taken in order to improve the amount of data transmitted in a unit time between apparatuses (or circuits) having data processing function.
However, if the amount of data transmission per unit time is to be increased by the former approach, the number of signal lines in and between data transmitters must be increased.
Accordingly, in the system employing an interface apparatus having increased amount of data transmission per unit time from this approach, the number of interconnections connecting the apparatuses (circuits), the number of signal lines in the apparatuses (circuits), the number of input/output terminals of the apparatuses (circuits) are increased, the scale of apparatuses (circuits) including IO drivers is increased incidentally, and therefore such system becomes large and expensive.
For example, referring to FIG. 39, assume that the data transmitter 920 is an integrated circuit device formed on the same chip as the data terminal equipment 902 and that the data transmitter 922 is an integrated circuit device formed on the same chip as the data terminal equipment 904. The number of IO pins of these integrated circuit device packages constituting the data signal lines DL1 to DLn is increased. Accordingly, since the number of signal lines between data holding mechanism 930 and output buffer 934 is increased, the area of the integrated circuit chip on which the transmitting side data transmitter 920 is formed is increased, and as the number of signal lines between data holding mechanism 950 and input buffer 950 is increased, the chip area of the integrated circuit in which the receiving side data transmitter 922 is formed is increased.
However, such increase in the chip area and in the number of input/output pins is not preferable as it goes against the recent demand of smaller and less expensive integrated circuit devices.
If the amount of data transmission per unit time is to be increased by the latter approach, it is necessary to increase the speed of data transmission between data transmitters. However, the speed of transmission is determined, as mentioned above, by the characteristics of data signal lines connecting data transmitters, the speed of signal processing in the transmitter side and receiver side data transmitters, the speed of data output from the transmitting side data transmitter and the speed of reception of data in the receiving side data transmitter.
Therefore, it becomes necessary to fabricate circuitry for generating various control signals, for example a clock signal, for controlling data transmission between data transmitters by using circuits which realize highly precise operation at higher speed. In addition, circuit condition such as impedance inductance and the like in the internal circuitry of the data transmitter must be more severely defined.
Accordingly, it becomes necessary to introduce elaborate and special circuit design technique and process technique. Therefore, it is not easy to increase the amount of data transmission per unit time by this approach.
As the data processing capability of information processing apparatuses used as data terminal equipment has been improved, the amount of data which can be processed at one time by the data terminal equipment has been increased. Therefore, when data transmission is carried out between such data terminal equipments having high data processing capability by using the conventional interface apparatus, the data terminal equipments cannot fully exhibit the inherent processing capability.
For example, referring to FIG. 53, assume that the CPUs 906 and 908 of data terminal equipments 902 and 904 are structured such that they can at one time process twice the data amount (n bits) which is transmitted at one time between data transmitters 920 and 922.
In that case, even if 2n bits of data are generated in CPU 906 of transmitting side data terminal equipment 902 to be transmitted to data terminal equipment 904, the 2n bits of data cannot be transmitted to data transmitter 922 from data transmitter 920 at one time but transmitted twice, n bits by n bits. Therefore, the 2n bits of data are transmitted by the interface apparatus 900 to data terminal equipment 904 consuming a time period corresponding to 2 cycle times of the transmission signal /CO.
Meanwhile, the CPU 908 on the receiving side data terminal equipment 904 is also structured to process at one time 2n bits of input data. Therefore, it can carry out data processing operation only at every time period corresponding to 2 cycle times of the transmission signals /CO.
More specifically, the receiving side data terminal equipment 904 cannot carry out the data processing operation from the supply of one word of data from the receiving side data transmitter 922 until the supply of the next one word of data and kept in the standby state. Therefore, the speed of data processing of the receiving side data terminal equipment 904 is, seemingly, about one half of the inherent speed of processing. Consequently, the speed of data processing of the entire system including the data terminal equipments 902 and 904 as well as the interface apparatus 900 is not much improved, though the capability of data processing of data terminal equipments 902 and 904 has been improved.
Therefore, in order to improve the speed of data processing of the entire system, it is desirable to much increase the amount of data transmission per unit time of the interface apparatus. In addition, even when the amount of data transmission per unit time is increased, the reliability of data transmission must be kept high.